The present invention relates generally to voltage clamping circuits, and more particularly to voltage clamping circuits that include low voltage devices.
Input/output (I/O) circuits are used to input and output electrical signals to and from integrated circuits and are usually coupled to one more I/O pins of an integrated circuit. I/o pins receive signals from external circuits and pass received signals to the corresponding I/O circuits. The I/O circuits pass the input signals to internal circuitry of the integrated circuit. I/O circuits also pass signals received from the integrated circuit's internal circuitry to the I/O pins, which in turn transmit these signals to external circuits.
One known voltage clamping circuit (described in U.S. Pat. No. 8,493,122) includes first and second voltage detection circuits, a plurality of transistors and an I/O pin. The I/O pin is protected from voltage overshoots by three transistors and the first voltage detection circuit and is protected from voltage overshoots by a further three transistors and the second voltage detection circuit.
A drawback of the known clamping circuit is that during positive voltage surges above the I/O supply voltage, the clamping mechanism transfers current from the I/O pin to the I/O supply. This can result in a slight upward shift in the I/O supply voltage value, which may be undesirable. Accordingly, it would be advantageous to providing a clamping circuit which did not exhibit this behavior.